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Paradigm Works® Development Services group has experts in Architecture, Design, Synthesis, Verification, and Test of ASICs/FPGAs. Our seasoned team has many years of leading edge design and verification experience. We help customers doing SoC designs, implementing new technologies like Rambus, IXP2800, etc., and those who need advanced support in using new tools from Verisity, Mentor, Cadence, or Synopsys. We specialize in processors, peripherals, Rambus memory, 3rd-party IP integration, and reuse.
Our expertise in functional verification of SoC designs is possibly as good as any independent organization in the world today. We have 100% satisfied customers including Sun Microsystems, Cisco, HP, Rambus, TranSwitch, and many others. We are based in Andover, MA USA (with offices in CA and the UK) and work onsite at our customers facilities for most projects.
Paradigm Works® Development Services support all phases of ASIC and FPGA development, including:
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Architecture
Chip architecture is all about a set of best practices that starts with a set of requirements. Paradigm Works®
Development Services teams help clients to deconstruct components, features, and functions, thereby ensuring good decisions at the Macro and Micro levels of chip architecture. We drill down into overall system requirements and assists your architects in making a great product. Our engineers will help you in the following architectural areas:
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- Hardware and software partitioning
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- ASIC/FPGA technology evaluation and mapping
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- Performance modeling/analysis
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- Third party intellectual property evaluation
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- Interface definitions
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- Memory Schemes
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- Board/Chip/Module level partitioning
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- I/O Analysis
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- Design Re-Use
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- Design for Test
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The engineers at Paradigm Works® can add real value to the Architecture phase of your project because of our domain expertise with both established and next generation technologies.
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Design
Paradigm Works® Development Services is backed by substantial experience in high end ASIC and FPGA design. We are VHDL/Verilog experts, and are well versed with the vast array of tools, technologies, methods, and details required to bring your ASIC and FPGA designs to fruition. We have worked on designs spanning a vast array of technologies (0.13u), protocols (ATM, Ethernet, DSL, OC192, etc.) vendors (TI, Toshiba, IBM, NEC, VTI, etc.), third party cores (ARM, PCI, USB, MAC, PHY, etc.), and application spaces (computers, networking, storage, graphics, video, ATE, etc.). There are a number of important considerations to realizing what we call "Maximum Design Effectiveness". These considerations include but are not limited to: Coding Guidelines, Reuse, Specification Templates, Database Revision Control, Foundry characteristics, etc. In many cases, Paradigm Works® Development Services may include actual tools in the form of documents or code to assist in the Design process. Our past successes can therefore greatly benefit your project.
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Synthesis/Timing Closure
In today's deep sub-micron silicon world, one of the biggest obstacles to time to market is synthesis and timing closure. Paradigm Works® Development Services teams have a deep understanding of synthesis and the problems associated with synthesizing deep sub-micron designs. We employ a structured approach to this problem by laying the groundwork early in the design cycle, including guidelines for HDL coding, partitioning, scripting, I/O clocking, and silicon technology. Further, Paradigm Works® teams can help reduce the traditional synthesis/timing closure iteration time by utilizing its experience with emerging physical synthesis tools and technologies.
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Verification
Paradigm Works® Development Services include tremendous depth and breadth of experience in design verification. Prior experience has taught us that up-front planning is the key to success. Everyone talks about methodology today but we know that more than languages, tools and techniques, methodology is planning, and more than anything else, planning is served by broad experience. Any reasonably complex chip and system development project undertaken today will involve more tools, design files, IP sources, engineers and engineering disciplines than ever before. Therefore the Paradigm Works® approach to design verification makes the most of diverse resources and minimizes project risk by concentrating the early work on planning and integration. We have the skills and experience to integrate all of the best-in-class solutions for your challenges.
Paradigm Works® Development Services teams have hands-on, hard-core experience with all of the following:
- Verification plans for communications systems, storage systems, computers, graphics systems and more
- Verification frameworks and languages such as Specman and Vera
- Socket-based verification platforms
- PLI / FLI interfaces
- All popular commercial simulators (and a few proprietary ones too)
- C/C++, Object Oriented design and programming, Perl, tcl, shell script, make, etc.
- Architectural, behavioral and cycle accurate modeling
- Transactor / verification component development
- Verilog, VHDL, some proprietary HDLs
- Hardware / software co-simulation including development of tools
- Formal Verification (rules-based model checking as well as equivalence checking)
- FPGA rapid prototyping
- Design and Verification database management, version control and configuration management
- Coverage measurement (code coverage and functional coverage)
- Load balancing systems (particularly LSF)
Large chip and system design verification is a multi-discipline endeavor that requires well thought out methodology and a holistic approach and it's certainly true today that one size does not fit all. Our experience with communications systems, computer designs, graphics systems and other technology areas as well as deep ASIC process knowledge enables our engineers to design environments and tests that maximize efficiency and effectiveness of each unique verification effort.
Chip Construction
Chip Construction is often one of the most underestimated, yet critical tasks in the ASIC development process. ASICs must eventually make the passage from the virtual "HDL" world into the real world of physical hardware. Paradigm Works® teams have the expertise, processes, and knowledge to take your ASICs through this very challenging transformation. Our Physical Design Methodology engineers can implement all Design for Test aspects of your devices, and are well versed in the areas of I/O construction, boundary scan insertion, JTAG, BIST, ATPG, equivalence checking, and timing closure.
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Foundry Support
An important aspect of Paradigm Works® Development Services is our ability to work with most of the world's leading semiconductor manufacturing companies. Fortunately, there are a good number of established foundries that offer both leading edge technology and reliable processes to support the manufacture of today's complex designs. Among them, Paradigm Works® engineers are fluent with and can support the following firms for ASIC development: TI, Toshiba, IBM, NEC, VTI. For FPGA's, we can provide important assistance for both Altera and Xilinx based designs.
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