Paradigm Works delivers state-of-the-art software and productivity accelerators to help our customers minimize their development time and accelerate the time to market of their innovations. Our dedicated team of expert developers has significant and relevant real-world advanced design, verification, and project methodology experience. We apply the power of the knowledge gained through our premier Development Services business to ensure our software products have an immediate and sustainable impact on our customer's product development efforts.
Paradigm Works currently provides SystemVerilog FrameWorks™ and ReleaseWorks™ software to maximize the productivity of FPGA & ASIC development teams.
SystemVerilog FrameWorks™ (SVF)
Built for SystemVerilog functional verification environments, SystemVerilog FrameWorks™ enables rapid project ramp-up by generating a project environment that is ready-to-go out of the box, complete with directory trees, run script templates, SystemVerilog base classes, and automated register handler class generation. In addition, to promote a functional coverage driven and constrained random based verification approach, a verification plan template is provided which goes hand in hand with the functional coverage tool. The verification plan template, along with the generated verification environment, register tool, and the functional coverage tool, enables your verification methodology to be standardized company-wide, ensures adherence to best-practice verification methods, and promotes reuse, scalability, and maintainability.
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One component of SVF is the SystemVerilog FrameWorks™ Template Generator utility, called SVF-TG. SVF-TG has been developed to assist in creating and maintaining SystemVerilog environments. Teams can utilize this tool to create customized templates of verification components such as transactors, environment classes, and the default directory structure for a given project. Please download the SVF-TG Whitepaper to see how SVF-TG can be used for your poject. The paper uses VMM as an example, but SVF-TG also supports AVM and URM.
Please give the free version of SVF-TG a try to generate SystemVerilog environments for your project!
ReleaseWorks™
ReleaseWorks™ is a release management and regression automation tool. As the front-end to ReleaseWorks™, the GVP module (Gather, Validate, & Publish) coordinates the database changes and regression process for your project. GVP performs "Gathers" (gather all the changed files), "Validates" (validate the integrity of the changes), and "Publishes" (propagate updated database to the user community) for your entire project repository. The ability to consistently and cleanly create releases of databases for team oriented development projects is a key determinant in project success.
As the backend to ReleaseWorks™ and also a stand alone module itself, the RRT module (Regression Results Tool) posts regression results and statistics to an internal project website for easy viewing by the entire project team.
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