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Title
Publication Type
Topic
Event
Year
Rev
Awards
A Unified and Simple Technique to Execute Both Sequences and Virtual Sequences
Paper
UVM
DVCON
2025
1.1 Mar 2025
uvmtb_template Files - An Efficient & Rapid Way To Create UVM Testbenches
Paper
UVM
SNUG Silicon Valley
2025
1.0 Apr 2025
Tech Paper Award 2nd Place
Understanding the UVM m_sequencer, p_sequencer Handles, and the `uvm_declare_p_sequencer Macro
Paper
UVM
SNUG Silicon Valley
2024
1.0 Apr 2024
Voted Best Paper 3rd Place
The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API
Paper
UVM
DVCON
2023
1.2 Mar 2023
UVM Virtual Sequences the Easy Way - (not the Hard Way or the other Hard Way!)
Paper
UVM
SNUG Silicon Valley
2023
1.0 Feb 2023
Voted Best Paper 3rd Place
13 Reason Why UVM and OVM are Hard to Learn
UVM
Cliff-Note #4
2022
1.1 June 2022
UVM Reactive Stimulus Techniques
Paper
UVM
DVCON
2020
1.0 Oct 2020
Voted Best Paper 1st Place
Finite State Machine (FSM) Deisgn & Synthesis using SystemVerilog - Part I
Paper
FSM
SNUG Silicon Valley
2019
1.0 Feb 2019
Voted Best Paper 1st Place
Yikes! Why is My SystemVerilog Still So Slooooow?
Paper
SystemVerilog
DVCON
2019
1.0 Apr 2019
Voted Best Paper 1st Place
SystemVerilog Virtual Classes, Methods, Interfaces and Their Use in Verification and UVM
Paper
UVM
SNUG Silicon Valley
2018
1.0 Jun 2018
Voted Best Paper 2nd Place
UVM Analysis Port Functionality and Using Transaction Copy Commands
Paper
UVM
SNUG Austin
2018
1.0 Oct 2018
Voted Best Paper 2nd Place
Applying Stimulus & Sampling Outputs - UVM Verification Testing Techniques (Paper explains why SystemVerilog "program" was a bad idea and should never be used)
Paper
UVM
SNUG Austin
2016
1.0 Jun 2018
SystemVerilog Assertions - Bindfiles & Best Known Practices for Simple SVA Usage
Paper
UVM
SNUG Silicon Valley
2016
1.0 Apr 2016
Voted Best Paper 1st Place
SystemVerilog Logic Specific Processes for Synthesis - Benefits and Proper Usage
Paper
SystemVerilog
SNUG Silicon Valley
2016
1.0 Apr 2016
Tech Paper Award 2nd Place
Using UVM Virtual Sequencers & Virtual Sequences
Paper
UVM
DVCON
2016
1.1 Sep 2019
Why Use Classes to Represent UVM Transactions?
UVM
Cliff-Note #5
2015
1.0 June 2015
How Do You Know When Your Test Is Broken? Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions
Presentation
SVA
SNUG Austin
2014
How Do You Know When Your Test Is Broken? Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions
Paper
SVA
SNUG Austin
2014
UVM Message Display Commands - Capabilities, Proper Usage and Guidelines
Paper
UVM
SNUG Austin
2014
1.2 Apr 2023
Voted Best Paper 1st Place
UVM Transactions - Definitions, Methods and Usage
Paper
UVM
SNUG Silicon Valley
2014
1.1 May 2014
Tech Paper Award 3rd Place
Migrating Verilog to UVM for FPGA Core Validation - Presentation
Presentation
UVM
DVCon
2013
OVM/UVM Scoreboards - Fundamental Architectures
Paper
UVM
SNUG Silicon Valley
2013
1.1a Oct 2014
Reset Testing Made Simple - Examples (tarfile)
UVM
SNUG Silicon Valley
2013
Reset Testing Made Simple with UVM Phases (Paper)
Paper
UVM
SNUG Silicon Valley
2013
Reset Testing Made Simple with UVM Phases (Slides)
Presentation
UVM
SNUG Silicon Valley
2013
The New SystemVerilog-2012 Standard (bw)
Presentation
SystemVerilog
DAC
2013
1.0 Jun 2013
The New SystemVerilog-2012 Standard (color)
Presentation
SystemVerilog
DAC
2013
1.0 Jun 2013
Are Advanced Verification Methodologies Required to Test FPGA Designs?
UVM
Cliff-Note #3
2012
1.0 Nov 2012
Conscious of Streams: Managing Parallel Stimulus
Presentation
UVM
DVCon
2012
Conscious of Streams: Managing Parallel Stimulus
Paper
UVM
DVCon
2012
Coverage Driven Verification
Presentation
Coverage
DVCon
2012
Integrating DesignWare USB3 Device Controller IP Into a UVM-based Testbench
Presentation
UVM
SNUG Silicon Valley
2012
Integrating DesignWare USB3 Device Controller IP Into a UVM-based Testbench
Paper
UVM
SNUG Silicon Valley
2012
Stacking UVCs Methodology
Presentation
UVM
DVCon
2012
Stacking UVCs Methodology
Paper
UVM
DVCon
2012
The OVM/UVM Factory & Factory Overrides How They Work - Why They Are Important
Paper
UVM
SNUG Silicon Valley
2012
1.2 Jan 2013
Automated Release Process…$Priceless
Paper
Release Management
DVCon
2011
Automated Release Process…$Priceless
Presentation
Release Management
DVCon
2011
OVM & UVM Techniques for Terminating Tests
Paper
UVM
DVCON
2011
1.1 Mar 2011
ReleaseWorks™
App Note
Release Management
General
2011
ReleaseWorks™ - Datasheet
Datasheet
Release Management
General
2011
SystemVerilog FrameWorks™ Scoreboard: An Open Source Implementation Using UVM
Presentation
UVM
DVCon
2011
SystemVerilog FrameWorks™ Scoreboard: An Open Source Implementation Using UVM
Paper
UVM
DVCon
2011
UVM Workshop – Verifying Blocks to IP to SOCs to Systems
Presentation
UVM
DAC
2011
Verification Works™ - Datasheet
Datasheet
Verification
General
2011
VerificationWorks™ - Build & Run
App Note
Process
General
2011
VerificationWorks™ - envBuilder
App Note
UVM
General
2011
VerificationWorks™ - RRT (Regression Report Tool)
App Note
Regressions
General
2011
VerificationWorks™ - Scoreboard
App Note
UVM
General
2011
VerificationWorks™ - Spec2Reg
App Note
Registers
General
2011
Increasing Verification Productivity with VMM Applications (RAL)
Presentation
VMM
DVCon
2010
Release Management A Problem You Cannot Afford To Ignore: 5 Steps to Automate
Paper
Release Management
SNUG San Jose
2010
Release Management A Problem You Cannot Afford To Ignore: 5 Steps to Automate
Presentation
Release Management
SNUG San Jose
2010
SystemVerilog-2009 Enhancements: Priority/Unique/Unique0
Paper
SystemVerilog
DVCon
2010
1.1 Jan 2012
Testbench Configuration Mantra
Presentation
SystemVerilog
DVCon
2010
Testbench Configuration Mantra
Paper
SystemVerilog
DVCon
2010
Common Mistakes In Technical Texts
Mistakes
Cliff-Note #2
2009
1.1 Mar 2009
Divide and Conquer: Techniques for Creating Highly Reusable Stimulus Generation Process
Paper
OVM,VMM
DVCon
2009
Divide and Conquer: Techniques for Creating Highly Reusable Stimulus Generation Process
Presentation
OVM,VMM
DVCon
2009
SystemVerilog Assertions Design Tricks & SVA Bind Files
Paper
SystemVerilog Assertions
SNUG San Jose
2009
1.0 Mar 2009
Voted Best Paper 1st Place
SystemVerilog's Virtual World - An Introduction to Virtual Classes, Veritual Methods and Virtual Interface Instances
Paper
SystemVerilog
SNUG Boston
2009
1.4 Sep 2009
Voted Best Paper 2nd Place
SystemVerilog-2009 Update - Part 1 - DAC Slides (bw)
Presentation
SystemVerilog
DAC
2009
1.1 Aug 2009
SystemVerilog-2009 Update - Part 1 - DAC Slides (color)
Presentation
SystemVerilog
DAC
2009
1.1 Aug 2009
SystemVerilog-2009 Update - Part 2 - DAC Slides (color)
Presentation
SystemVerilog
DAC
2009
1.1 Aug 2009
Using the New Features in VMM 1.1 for Multi-Stream Scenarios
Paper
VMM
SNUG San Jose
2009
1.0 Mar 2009
Tech Paper Award 2nd Place
Building Reusable Verification Environments with OVM
Article
OVM,VMM
EDA Tech Forum
2008
Clock Domain Crossing (CDC) Design & VerificationmTechniques Using SystemVerilog
Paper
CDC
SNUG Boston
2008
1.0 Nov 2008
Voted Best Paper 1st Place
Generating VMM Compliant Environments
Presentation
VMM
Synopsys Interop
2008
Generating VMM Compliant Environments with SystemVerilog FrameWorks™ Template Generator (SVF-TG)
Paper
VMM
White Paper
2008
Migrating AVM & URM to OVM - CDNLive! Munich
Presentation
OVM
CDNLive! Munich
2008
Migrating AVM & URM to OVM - CDNLive! Silicon Valley
Paper
OVM
CDNLive! Silicon Valley
2008
Migrating AVM & URM to OVM - CDNLive! Silicon Valley
Presentation
OVM
CDNLive! Silicon Valley
2008
Migrating AVM & URM to OVM - Mentor User2User
Paper
OVM
Mentor User2User
2008
Migrating AVM & URM to OVM - Mentor User2User
Presentation
OVM
Mentor User2User
2008
Migrating AVM to OVM - Mentor User Group Boston
Presentation
OVM
MUG Boston
2008
SystemVerilog Implicit Port Enhancements Accelerate System Design & Verification
Paper
SystemVerilog
DAC
2008
1.1 Nov 2008
SystemVerilog's Virtual World - An Introduction to Virtual Classes, Veritual Methods and Virtual Interface Instances
Paper
SystemVerilog
SNUG Boston
2008
1.1 xx 2008
A VMM Based Generic Interrupt Handling Mechanism
Presentation
VMM
SNUG San Jose
2007
A VMM Based Generic Interrupt Handling Mechanism
Paper
VMM
SNUG San Jose
2007
Generating and Maintaining AVM-based Verification Environments
Presentation
AVM
DVCon
2007
Getting the Most Out of Functional Coverage Tips and Techniques
Paper
Coverage
SNUG San Jose
2007
Managing Functional Coverage
Presentation
Coverage
DesignCon
2007
Module or Class-Based uRM? A Pragmatic Guide to Creating Verification Environments in SystemVerilog
Presentation
UVM
CNDLive Silicon Valley
2007
Module or Class-Based uRM? A Pragmatic Guide to Creating Verification Environments in SystemVerilog
Paper
UVM
CNDLive Silicon Valley
2007
SystemVerilog Implicit Port Enhancements Accelerate System Design & Verification
Paper
SystemVerilog
SNUG Boston
2007
1.1 Nov 2007
Voted Best Paper 1st Place
The Sunburst Design - "Where's Waldo" Principle of Verilog Coding
RTL
Cliff-Note #1
2007
1.0 Mar 2007
Detecting End-of-Test Conditions - A Shutdown Manager Implementation for an AVM-based Verification Environment
Article
AVM
Verification Horizons
2006
Formal Verification Techniques
Presentation
Formal
General
2006
Getting off the Ground When Creating an RVM Testbench
Presentation
RVM
SNUG San Jose
2006
Getting off the Ground When Creating an RVM Testbench
Paper
RVM
SNUG San Jose
2006
Is My Test Done? SystemVerilog Shutdown Manager
Presentation
SystemVerilog
CDNLive! Nice, France
2006
Reusing Verification Components in System-Level Modeling Environments
Presentation
Reuse
HPEC
2006
Reusing Verification Components in System-Level Modeling Environments
Paper
Reuse
HPEC
2006
Risk Reduction in a Verification Upgrade
Article
OVM
EDN
2006
Solutions for PCI Express Design Verification
Article
PCIe
Embedded Computing Design
2006
SystemVerilog Event Regions, Race Avoidance & Guidelines
Paper
SystemVerilog
SNUG Boston
2006
1.2 Dec 2007
Augmenting a C++/PLI/VCS Based Verification Environment with SystemC
Paper
HVLs
SNUG San Jose
2005
Augmenting a C++/PLI/VCS Based Verification Environment with SystemC
Presentation
HVLs
SNUG San Jose
2005
SystemVerilog Implicit Port Connections - Simulation & Synthesis
Paper
SystemVerilog
DesignCon
2005
1.2 Apr 2005
SystemVerilog's priority & unique - A Solution to Verilog's "full_case" & "parallel_case" Evil Twins!
Paper
SystemVerilog
SNUG Israel
2005
1.0 Jan 2005
Advanced Encapsulation - A Panacea for Reducing the Support Burden?
Presentation
Specman
Verisity ClubV USA
2004
Crossing the Abyss: Asynchronous Signals in a Synchronous World
Article
CDC
EDN
2004
Multilayered IP for System Level Verification
Presentation
Specman
DVCon
2004
SystemVerilog 2-State Simulation Performance & Verification Advantages
Paper
SystemVerilog
SNUG Boston
2004
1.0 Sep 2004
Asynchronous & Synchronous Reset Design Techniques - Part Deux
Paper
CDC
SNUG Boston
2003
1.3 Jul 2004
At Speed Testing with Scan Vectors - Article
Article
ATPG
EEdesign.com
2003
Creating Useful Coding Guidelines For A Verification Environment
Paper
Guideline
DVCon
2003
Multilayered Advanced eRM Architecture for Ethernet eVC - Verisity ClubV Japan
Presentation
Specman
Verisity ClubV Japan
2003
Multilayered Advanced eRM Architecture for Ethernet eVC - Verisity ClubV Ottawa
Presentation
Specman
Verisity ClubV Ottawa
2003
Multilayered Architecture for PCI Express eVC
Presentation
Specman
General
2003
Synthesizable Finite State Machine Design Techniques Using the New SystemVerilog 3.0 Enhancements
Paper
FSM
SNUG San Jose
2003
1.1 Mar 2003
Voted Best Paper 2nd Place
SystemVerilog for VHDL Users
Paper
SystemVerilog
SNUG Boston
2003
1.2 Apr 2004
Voted Best Paper 3rd Place
The IEEE Verilog-2001 Simulation Tool Scoreboard
Paper
Verilog
DVCON
2003
1.2 Apr 2003
Top 10 Dos & Don'ts for Open Vera Assertions
Paper
Assertions
SNUG Boston
2003
Top 10 Dos & Don'ts for Open Vera Assertions
Presentation
Assertions
SNUG Boston
2003
Using Mentor FastScan to Generate At Speed Scan Vectors
Paper
ATPB
General
2003
Assertive Verification: A Ten-Minute Primer
Article
Assertions
EEdesign.com
2002
Development of a PCI Express Coverage Monitor eVC
Presentation
Specman
Verisity ClubV USA
2002
Integrating Third Party Tools Using C Interface
Presentation
Specman
Verisity ClubV USA
2002
New Verilog-2001 Techniques for Creating Parmeterized Models (or Down With `define and Death of a defparam!)
Paper
Verilog
HDLCON
2002
1.2 May 2002
Simulation and Synthesis Techniques for Asynchronous FIFO Design (recommended)
Paper
CDC
SNUG San Jose
2002
1.3 Nov 2005
Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons
Paper
CDC
SNUG San Jose
2002
1.3 Aug 2020
Voted Best Paper 1st Place
Specman Functional Coverage In the Context of an eVC
Presentation
Specman
Verisity ClubV USA
2002
Synchronous Resets? Asynchronous Resets? I am so Eventused! How will I ever know which to use?
Paper
CDC
SNUG San Jose
2002
1.1 Apr 2002
SystemVerilog Ports & Data Types For Simple, Efficient and Enhanced HDL Modeling
Paper
SystemVerilog
HDLCON
2002
1.1 Apr 2002
The Fundamentals of Efficient Synthesizable Finite State Machine Design using NC-Verilog and BuildGates
Paper
FSM
International Cadence Users Group (ICU)
2002
1.4 Jul 2002
Voted Best Paper 2nd Place - ICsig
Using Specman Elite to Verify a 6-Port Switch ASIC
Presentation
Specman
HDLCon
2002
Using Specman Elite to Verify a 6-Port Switch ASIC
Paper
Specman
HDLCon
2002
Verilog Nonblocking Assignments With Delays, Myths & Mysteries
Paper
Verilog
SNUG Boston
2002
1.4 May 2003
Voted Best Paper 2nd Place
Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs
Paper
CDC
SNUG San Jose
2001
1.2 Jun 2005
Voted Best Paper 3rd Place
Verilog-2001 Behavioral and Synthesis Enhancements
Paper
Verilog
HDLCON
2001
1.3 Apr 2002
A Proposal To Remove Those Ugly Register Data Types From Verilog
Paper
Verilog
HDLCON
2000
1.1 Mar 2001
Coding And Scripting Techniques For FSM Designs With Synthesis-Optimized, Glitch-Free Outputs
Paper
FSM
SNUG Boston
2000
1.2 May 2002
Voted Best Paper 2nd Place
Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!
Paper
Verilog
SNUG San Jose
2000
1.4 Jul 2016
Voted Best Paper 1st Place
"full_case parallel_case", the Evil Twins of Verilog Synthesis
Paper
Verilog
SNUG Boston
1999
1.1 Oct 2000
Voted Best Paper 1st Place
Correct Methods For Adding Delays To Verilog Behavioral Models
Paper
Verilog
HDLCON
1999
1.1 Mar 2001
fsm_perl: A Script to Generate RTL Code for State Machines and Synopsys Synthesis Scripts
Paper
FSM
SNUG San Jose
1999
1.1 Sep 2001
RTL Coding Styles That Yield Simulation and Synthesis Mismatches
Paper
Verilog
SNUG San Jose
1999
1.1 Oct 2000
State Machine Coding Styles for Synthesis
Paper
FSM
SNUG San Jose
1998
1.1 Sep 2002
High-Level Verilog Enhancements (bw)
Paper
Verilog
SNUG San Jose
1997
1.0 Feb 1997
High-Level Verilog Enhancements (color)
Paper
Verilog
SNUG San Jose
1997
1.0 Feb 1997
Verilog Coding Styles For Improved Simulation Efficiency
Paper
Verilog
International Cadence Users Group (ICU)
1997
1.1 Jan 2002
Voted Best Paper 1st Place - CAEsig
Passive Device Verilog Models For Board And System-Level Digital Simulation
Paper
Verilog
International Cadence Users Group (ICU)
1993
1.1 Oct 2004
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